Most digital circuits have a single or a few clock signals that determine the pace at which the functional units of the system work to guarantee proper communication among them. These circuits are called synchronous. The clock signal of a synchronous circuit is characterized by a high load capacitance and, thus, the propagation of the transitions of the clock signal may take a significant amount of time, if not done properly. The time difference among the arrival of the clock at different points of the circuit is known as clock skew. For a correct functioning of a synchronous circuit, clock skew is maintained within a certain small interval.
As the number of gates in digital circuits grows, the reduction of the clock skew becomes a difficult problem to solve. Circuits typically have complex clock networks aimed at the fast propagation of clock transitions with a small skew. Due to the high capacitance of the clock signal, these networks consume a significant amount of energy.
For example, several different schemes can be used to maintain a small skew when distributing clock signals in a circuit. A method that implements H-trees is used in full-custom layout. This method uses an H-shaped wiring scheme so that all paths from the clock driver to the end points of the signal have a similar length. Buffering trees, which are used in synthesis, placement and routing-based design flows, can be generated by synthesis tools in order to achieve a pre-determined maximum skew between any pair of flip-flop clock edges. Zero-skew routing is a technique used in place-and-route tools, which artificially lengthens some paths, in a bottom-up fashion from the flip-flops, in order to equalize path lengths. It is most effective when coupled with buffering. Techniques based on clock skew scheduling rely on an accurate timing analysis of the system and a schedule of fine-grain operations (e.g. gate-level operations) to maintain an acceptable skew of the clock in different points of the circuit.
However, each of these solutions faces the clock skew problem at different levels. In these previous examples, the clock skew problem is tackled by either reducing it by means of physical techniques, or by accurately calculating it and scheduling operations in such a way that the skew does not affect the correctness of synchronization.